1. Field of the Invention
The present invention relates to a semiconductor device, in particular, to a semiconductor device with a well wherein a scaling down of the layout is achieved.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as xe2x80x9cDRAMxe2x80x9d) will be described as an example of a conventional semiconductor device. FIGS. 17 and 18 show a border part between a memory cell region B and a peripheral circuit region A (sense amplifiers), and a region in the vicinity thereof, in a DRAM.
As shown in FIGS. 17 and 18, a shallow P well 123 and a deep P well 124 are, respectively, formed in the surface of a P type semiconductor substrate 101. A deep bottom N type well 102 is formed in a region beneath shallow P well 123 and deep P well 124. In addition, an N well 121 is formed in the surface of P type semiconductor substrate 101 adjoining a side of shallow P well 123.
A connection N well 122 is formed in a region between N well 121 and deep bottom N type well 102 so as to electrically connect the two. In addition, a shallow P well 120 is formed in a region on the side opposite to shallow P well 123 with N well 121 placed between them.
Shallow P well 123 and deep P well 124 are surrounded by N well 121, deep bottom N type well 102 and connection N well 122, and, thereby, a potential different from that of shallow P well 120 is applied thereto. In this case, a P+ type region 130 is formed in the surface of shallow P well 120 so that a ground potential (GND) is applied to this P+ type region 130. Then, a P+ type region 132 is formed in the surface of shallow P well 123 so that a potential (VBB) that is different from the ground potential is applied to this P+ type region 132. In addition, an N+ type region 131 is formed in the surface of N well 121 so that a predetermined potential (VPP) that is different from the other two potentials is applied to this N+ type region 131.
A transistor that includes N-+ type source and drain regions 139a and 139b as well as a gate electrode part 140 is formed on the surface of deep P well 124. This transistor is a memory cell transistor in memory cell region B.
A transistor that includes P+ type source and drain regions 135a and 135b as well as a gate electrode part 136 is formed on the surface of N well 121. A transistor that includes N+ type source and drain regions 137a and 137b as well as a gate electrode part 138 is formed on surface of shallow P well 123. These transistors are transistors in the peripheral circuit region (sense amplifiers).
Next, FIGS. 19 and 20 show a border part between a memory cell region B and a peripheral circuit region A (word line drivers), and a region in the vicinity thereof, in a DRAM. As shown in FIGS. 19 and 20, a shallow P well 123, a deep P well 124, an N well 121, a deep bottom N type well 102, a connection N well 122 and a shallow P well 120 are, respectively, formed in a P type semiconductor substrate 101 in the same manner as is each well shown in FIG. 18.
A P+ type region 150 is formed in the surface of shallow P well 120 so that a ground potential (GND) is applied to this P+ type region 150. Then, a P+ type region 152 is formed in the surface of shallow P well 123 so that a potential (VBB) which is different from the ground potential is applied to this P+ type region 152. In addition, an N+ type region 151 is formed in the surface of N well 121 so that a predetermined potential (VPP) that is different from the other two potentials is applied to this N+ type region 151.
A transistor that includes Nxe2x88x92 type source and drains regions 139a and 139b as well as a gate electrode part 140 is formed on the surface of deep P well 124. This transistor is a memory cell transistor in memory cell region B.
A transistor that includes N+ type source and drain regions 162a and 162b as well as a gate electrode part 163 is formed on the surface of shallow P well 123. A transistor that includes N+ type source and drain regions 160a and 160b as well as a gate electrode part 161 is formed on the surface of shallow P well 120. These transistors are transistors in peripheral circuit region A (word line drivers).
In this manner, in the above described DRAM, shallow P well 123 is surrounded by N well 121, deep bottom N type well 102 and connection N well 122 and, thereby, a predetermined potential (VBB) that is different from the potentials applied to shallow P well 120 or to N well 121 is applied thereto. This predetermined potential (VBB) is applied to P+ type regions 132 and 152 which are formed in shallow P well 123. In addition, because deep P well 124 and shallow P well 123 are formed so as to partially overlap each other, the two are electrically connected and the potential of deep P well 123 is also fixed at predetermined potential (VBB).
On the other hand, P well 120 is fixed at the ground potential. P well 120 is formed in a region outside of the region which is surrounded by and includes N well 121, deep bottom N type well 102 and connection N well 122 and is formed so as to adjoin a series of deep N type wells including N well 121, connection N well 122 and deep bottom N type well 102.
In the above described conventional DRAM, however, the following problems arise.
As described above, in order to apply a predetermined potential (VBB) to shallow P well 123 and to deep P well 124, P+ type regions 132 and 152 are formed in shallow P well 123 for the application of that potential. Therefore, it is necessary to secure a region for forming these P+ type regions 132 and 152 in shallow P well 123.
In addition, at the time when forming these P+ type regions 132 and 152, it is necessary to secure predetermined spaces between the N+ type source and drain regions 132a, 162a of the transistor, located in the vicinity thereof, and P+ type region 132. Then, it is necessary to secure a predetermined space between N well 121 located in the vicinity of P+ type region 132 and P+ type region 132 itself.
As a result, there is a limit to the scaling down of the area occupied by shallow P well 123 in P type semiconductor substrate 101 and this has become one factor that hampers the scaling down of the layout of a DRAM.
In addition, as described above, P well 120 is formed so as to adjoin a series of deep N type wells including N well 121, connection N well 122 and deep bottom N type well 102. Deep bottom N well 102 and connection N well 122 are formed by injecting ions of a predetermined conductive type, such as phosphorous, into P type semiconductor substrate 101. At this time, dispersion of the location where the well is formed occurs in the case of a comparatively deep well due to the relationship between the dispersion of the direction of ion injection and the depth of the well. Therefore, in order to maintain electrical insulation, it is necessary to secure a predetermined distance, space X, between P+ type region 130 formed in shallow P well 120 and the adjoining series of N wells (or the end part of shallow P well 120).
As a result, there is a limit to the reduction of space X between P+ type region 130 and the series of N wells and this has become another factor that hampers the scaling down of the layout of a DRAM.
The present invention is provided in order to solve the above described problems and has the purpose of providing a semiconductor device wherein a scaling down of the layout can be easily achieved.
One semiconductor device according to the present invention includes a semiconductor substrate of a first conductive type that has a main surface, a first well region of the first conductive type, a second well region of the first conductive type and a first voltage application part. The first well region of the first conductive type is formed at a predetermined depth from the main surface of the semiconductor substrate and is provided with a first semiconductor element. The second well region of the first conductive type is formed so as to partially overlap an edge part of the first well region in the main surface of the semiconductor substrate and is provided with a second semiconductor element that is placed shallower than the first well region. The first voltage application part is formed in a region where the first well region and the second well region overlap and a voltage is applied thereto in order to fix the first well region and the second well region at a predetermined potential.
In this configuration, the voltage application part is formed in a region where the first well region and second well region overlap and, thereby, the region for forming such first voltage application part can be eliminated from the second well region, in contrast to the case where such first voltage application part is formed in the second well region, so that the distance between the second semiconductor element and the edge part of the second well region can be reduced. As a result, the scaling down of the layout of a semiconductor device can be achieved.
It is preferable for the impurity concentration of the region where the first well region and the second well region overlap and where such first voltage application part is formed to be higher than the impurity concentration of the first well region and the second well region from which the overlapping region is eliminated.
Thereby, a predetermined potential can be applied without fail from the first voltage application part to the first well region and the second well region through the overlapping region without having an interim part where the electrical resistance is high.
In addition, preferably, the first semiconductor element is a memory cell transistor in a memory cell of a dynamic random access memory, while the second semiconductor element is a transistor arranged in the periphery of the memory cell.
In this case, the memory cell transistor is formed in the first well region which is deeper than the second well region while the transistor arranged in the vicinity of the memory cell is formed in the second well region. Thereby, particularly a leak current from the first well region to the to a region outside thereof or a leak current from the memory cell transistor to the first well region decreases so that the data maintenance characteristics of the memory cell improve.
More preferably, a third well region of the first conductive type formed in the main surface of the semiconductor substrate on the side opposite to the first well region at a distance from the second well region, a fourth well region of the second conductive type formed in a region ranging, at least, from the surface of a region of the semiconductor substrate located between the second well region and the third well region to a region of the semiconductor substrate located beneath the first well region and the second well region in order to electrically insulate the first and the second well regions from the third well region, and a second voltage application part, which is formed in the third well region and to which a voltage for fixing the third well region at a predetermined potential is applied, are provided wherein the deeper part of the fourth well region located on the side of the third well region is recessed in the direction away from the third well region.
In this case, the depth of the fourth well region becomes shallower in the part adjoining the third well region than it is in the other parts. Thereby, the dispersion of the location of the fourth well region decreases at the time when the fourth well region is formed so that the distance between the second voltage application part formed in the third well region and the edge part of the third well region can be shortened. Thereby, an additional scaling down of the layout can be achieved.
Concretely, it is preferable for the distance from the third well region to the recessed part located deeper in the fourth well region to be a distance where no current leaks between the region of the semiconductor substrate located beneath the third well region and the region of the semiconductor substrate located between the second well region and the fourth well region.
In this case, the scaling down of the layout of the semiconductor device can be achieved without affecting the operations of the first semiconductor element and the second semiconductor element under the condition where the first and the second well regions and the third well region are fixed, respectively, at different potentials.
Another semiconductor device according to the present invention is provided with a semiconductor substrate of a first conductive type which has a main surface, a first well region of the first conductive type, a voltage application part and a second well region of a second conductive type. The first well region of the first conductive type is formed at a predetermined depth from the main surface of the semiconductor substrate. The voltage application part is formed in the first well region and a voltage is applied for fixing the first well region at a predetermined potential. The second well region of the second conductive type is formed in the main surface of the semiconductor substrate so as to adjoin the first well region and is deeper than the first well region. Then, the deeper part of the second well region located on the side of the first well region is recessed in the direction away from the first well region.
In this configuration the depth of the second well region becomes shallower in the part adjoining the first well region than it is in the other parts. Thereby, the dispersion of the location of the second well region decreases at the time when the second well region is formed so that the distance between the voltage application part formed in the first well region and the edge part of the first well region can be shortened. As a result, the scaling down of the layout of the semiconductor device can be achieved.
The second well region is preferably formed so as to surround a predetermined region in the semiconductor substrate from above, from the main surface, and from below, from the inside of the semiconductor substrate, in order to electrically insulate the predetermined region from the first well region, and the distance from the first well region to the recessed part located deeper in the second well region is a distance where no current leaks between the region in the semiconductor substrate located beneath the first well region and the predetermined region.
In this case, the scaling down of the layout of the semiconductor device can be achieved without affecting the operations of an element formed in, for example, the predetermined region under the condition where the first well region and the predetermined region are fixed, respectively, at different potentials.
As a more concrete form of the second well region, it is desirable for the second well region to include an upper well region located in the vicinity of the main surface, a bottom well region that extends toward the side opposite to the first well region side and that is formed in a region at a predetermined depth from the main surface and a connection well region for electrically connecting the upper well region and the bottom well region wherein the part located deeper includes parts of the bottom well region and the connection well region.